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21 x ANALOG DEVICES ADSP-TS201SABP-060 DSP Floating-Point 32bit 600 MHz BGA 576, US $430 – Picture 0
21 x ANALOG DEVICES ADSP-TS201SABP-060 DSP Floating-Point 32bit 600 MHz BGA 576, US $430 – Picture 0

21 X Analog Devices Adsp-ts201sabp-060 Dsp Floating-point 32bit 600 Mhz Bga 576

US $430

  • Lachine, QC, Canada
  • Jun 12th
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21 x ANALOG DEVICES   ADSP-TS201SABP-060 DSP  Floating-Point 32bit  600 MHZ, BGA 576 Here's some spec: The ADSP-TS201 processor is a 128-bit, high performance TigerSHARC processor. The ADSP-TS201 processor sets a new standard of performance for digital signal processors, combining multiple computation units for floating-point and fixed-point processing as well as very wide word widths. The ADSP-TS201 processor maintains a ‘system-on-chip’ scalable computing design philosophy, including 24M bit of on-chip DRAM, six 4K word caches (one per memory block), integrated I/O peripherals, a host processor interface, DMA controllers, LVDS link ports, and shared bus connectivity for glueless multiprocessing.   In addition to providing unprecedented performance in DSP applications in raw MFLOPS and MIPS, the ADSP-TS201 processor boosts performance measures such as MFLOPS/Watt and MFLOPS/square inch in multiprocessing applications. The processor has the following architectural features:   • Dual computation blocks: X and Y – each consisting of a multiplier,    ALU, CLU, shifter, and a 32-word register file • Dual integer ALUs: J and K – each containing a 32-bit IALU and    32-word register file • Program sequencer – Controls the program flow and contains an    instruction alignment buffer (IAB) and a branch target buffer    (BTB) • Three 128-bit buses providing high bandwidth connectivity    between internal memory and the rest of the processor core (compute    blocks, IALUs, program sequencer, and SOC interface) • A 128-bit bus providing high bandwidth connectivity between    internal memory and external I/O peripherals (DMA, external    port, and link ports) • External port interface including the host interface, SDRAM controller,    static pipelined interface, four DMA channels, four LVDS    link ports (each with two DMA channels), and multiprocessing    support • 24M bits of internal memory organized as six 4M bit blocks—each    block containing 128K words x 32 bits; each block connects to the    crossbar through its own buffers and a 128K bit, 4-way set associative    cache • Debug features • JTAG Test Access Port If you have questions, email us.

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