240 X Ic Fujitsu Mb87f3191pb G Bsc Asic Bga352

US $430

Lachine, QC, Canada
Jun 13th

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240 x IC FUJITSU MB87F3191PB G ASIC BGA352 These are hard to find parts; we have them in stock for: Here's some spec: 1. General Description 1.1 BSC ASIC Block Diagram Description The Top Level Block Diagram shows the two major functional blocks within the BSC ASIC, the CellMAC Controller and the Request Processor. In the Down Stream (DS) direction, the CellMAC Controller block takes ATM cells from the TX Utopia port, frames them by adding MAC overhead to the beginning of the cell and Forward Error Correction (FEC) bits to the end of the cell, and sending the resulting packet to one of the BMU channels. In the Up Stream (US) direction, packets are received from a BMU channel, errors are checked and corrected, the MAC overhead is stripped, and the resulting ATM cells are delivered to the RX Utopia port. Cells may optionally be encrypted and decrypted using the Data Encryption Standard (DES). 56-bit DES keys are supported, but the ASIC also has a pad-selectable mode to limit keys to 40 bits for export. If the DesMode pad is not bonded to a pin, or if the pin is not pulled low, the chip only works in 40-bit-key mode. The CellMAC Controller block uses one external 128kx8 SRAM to hold error statistics, and another 128kx8 SRAM to hold DES keys. The Request Processor determines which Subscriber Access System (SAS) is granted (allowed to transmit) on a slot-by-slot basis. The grants may be periodic, to support Constant Bit Rate (CBR) services, or on demand, to support Variable Bit Rate (VBR) services. Grants are passed to the CellMAC Controller block, which includes them in the DS overhead. A SAS may request bandwidth for VBR services by embedding requests in the overhead of cells it transmits up stream. The CellMAC Controller will extract the requests and present them to the Request Processor. The AirStar system also supports a contention mechanism to allow a SAS to request bandwidth independent of US cell transmission, as well as a mechanism to admit a SAS into the network. The Request Processor uses an external SRAM array to contain Traffic Management Records (TMRs) and control queues. Both blocks share a microprocessor interface. This interface allows software to create and tear down connections, specify encryption keys, gather error statistics, and configure the ASIC hardware. Email us for more info.