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324 x IC XILINX XC17256EPD8I PROM (DIP8) Serial Configuration OTP 256Kx1, US $79 – Picture 0
324 x IC XILINX XC17256EPD8I PROM (DIP8) Serial Configuration OTP 256Kx1, US $79 – Picture 0

324 X Ic Xilinx Xc17256epd8i Prom (dip8) Serial Configuration Otp 256kx1

US $79

  • Lachine, QC, Canada
  • May 31st
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324 x IC XILINX XC17256EPD8I PROM  (DIP8) Serial Configuration OTP 256Kx1   Serial Configuration Proms for Xilinx FPGA Devices Here's some spec: GENERAL DESCRIPTION: XC1700E Family of Serial Configuration PROMs Features • Serial Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Simple interface to the FPGA requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • The XC17128E/EL and XC17256E/EL devices support the XC4000EX/XL/XLA/XV fast configuration mode (15.0 MHz) • Low-power CMOS floating gate process • Available in 5 V and 3.3 V versions • Available in compact plastic 8-pin DIP, 8-pin SOIC, 8-pin VOIC, or 20-pin PLCC packages. • Programming support by leading programmer manufacturers. • Design support using the Xilinx Alliance and Foundation series software packages.   Description The XC1700 family of serial configuration PROMs (SPROMs) provides an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the SPROM. A short access time after the rising clock edge, data appears on the SPROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the SPROM. When the FPGA is in Slave Serial mode, the SPROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all SPROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the FPGA design file into a standard HEX format which is then transferred to most commercial PROM programmers   We have 1 Reels in Stock Now. 1 Box of Qty: 324 Parts. If you have questions, email us.

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