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JESD204 A/B IP Core for XILINX Kintex /ALTERA, US $450.00 – Picture 0
JESD204 A/B IP Core for XILINX Kintex /ALTERA, US $450.00 – Picture 1
JESD204 A/B IP Core for XILINX Kintex /ALTERA, US $450.00 – Picture 0
JESD204 A/B IP Core for XILINX Kintex /ALTERA, US $450.00 – Picture 1

Jesd204 A/b Ip Core For Xilinx Kintex /altera

US $450.00

  • Riga, Latvia
  • Jan 29th
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 Hallo! For selling a ISE JESD204 IP Core Project for Kintex 7    ( Artix/Virtex and other FPGA possible too, after reconfiguration ) it was made by developers for our data acquisition board ( ADC 250 Msps to FPGA through JESD204b serial lanes)IP Core supports all JESD204B Subclasses is the deterministic latency You can receive data from ADC and send to DAC, configure it for your application. No I/O lanes limitation  Same Core price range 7 000 - 20 000 usd depending on the functional Please find by Google  " EF-DI-JESD204-SITE " Project written on Verilog and you can easy to configure  as an example  module jesd204_v2_2_top # ( parameter C_ELABORATION_TRANSIENT_DIR = "blank", parameter C_COMPONENT_NAME = "blank", parameter C_FAMILY = "virtex7", parameter C_NODE_IS_TRANSMIT = 0, parameter C_LANES = 1, parameter C_JESD204B = 0, parameter C_DEVICE_SUBCLASS = 0, ... I ll provide technical support ( answers to your specifications) ., ask please before bidding Modelsim testbench picture shows the operation of the JESD CORE  rx_aclk = 125MHz  rx0_tdata, 32bit data bus from adc ( 2x14 bit)  rx0_tvalid, lanes 1 status  rx1_tdata, 32bit data bus ( 2x14bit)  rx1_tvalid lanes 2 status -------- Since a lot of people ask me: " I intrested start my project with your IP JESD, but not sure I can handle" my answer for all - if you know Verilog at the average level - you can configure IP JESD for your hardware, GTX/GTP pins, Sync and clock. This IP Core absolutely stable and has the greatest functionality and settings. Buyers receive support -  AXI init codes for IP programming and etc...  If you still can't use IP , you can send your project design and specification me., and our engineers ( for 100- 200 usd and up,depending on the complexity ) ?ustomize it . If  still does not work our IP - I refund your money. -------- ALSO, I suggest development of other FPGA Cores, PCB design ( FPGA+DSP), VHDL configuration, A great experience, many ready devices ( Avionics, radar, wireless com, etc...) We have RF / Patch Antenna Array  labs devices up to 40 GHz Please ask your system complete development Thank You

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