Mentor Embedded Performance MAJIC MX JTAG Interface box EPI JEENI JTAG Ethernet We gladly ship worldwide! Embedded Performance MAJIC MX JTAG Interface Controller with Manual MAJICMX Multi -Tap -Processor -Session Debug -Context/Thread -Architecture On-Chip Trace MAJIC-MX Multi-processor Advanced JTAG Interface Controller with MDSS MAJIC-MX MDSS Development System Features: * Ideal for multiple core SoC applications * Provides EPI MDSS technology * Supports execution tracing with on-chip trace buffers * FLASH memory programming support * Supports a wide choice of on-chip debug interfaces * Supports a wide variety of CPU cores * Supports on-chip hardware breakpoints * Unlimited software breakpoints * Programmable JTAG clock (TCK = 0 to 40 MHz) * Programmable trigger-in and trigger-out connections * Ethernet and serial I/O ports for fast, flexible host interface * High-speed download of application code * Network compatibility allows shared and remote operation * Internal RISC Processor provides on-probe intelligence * Wide selection of Configuration Kits extends usage to multiple architectures * Sleep-mode support * LEDs display operation status * Operates with most third party debuggers via industry standard APIs * Optional EDB integrated debugger * Interfaces for popular OS environments Product Information Finally a non-intrusive debug solution for your multiple core SoC and high CPU pipeline speed designs. Now, you can have the same level of control and visibility of the embedded CPU as you would with in-circuit emulators in traditional discrete CPU designs. The result is faster software integration, better testing, and improved time to market. The MAJIC-MX probe is the latest model in the MAJIC Series of intelligent debug probes. The series now supports scaling of SoC devices to unlimited clock rates and to unlimited number of on-chip cores. MAJIC-MX probe embodies the new EPI MDSS debug concept. This concept allows fast integration and debugging of software for complex SoC devices. It recognizes that SoC designs are rapidly scaling up in both pipeline speeds and complexity. Thus, MDSS supports: Multi-tap devices, Multi-core devices, Multi-architecture environments, Multi-session debug, Multi-context CPUs, and On-chip trace buffers. The MAJIC-MX probe provides a high-speed hardware interface between processors with an on-chip debug interface and industry standard debuggers. It is available with a choice of EPI debuggers and may be used with used with task-aware debuggers from leading OS vendors. The unit is self-contained in a small case approximately 2 x 6.5 x 7.5 inches in size. The non-intrusive MAJIC-MX probe communicates with the CPU core by JTAG interface using the existing boundary scan pins. For most on-chip debug facilities, it uses no target memory and requires no porting to the target system. Complete processor control means you can start, stop and single-step execution; read and write to registers, memory, and system I/O; and download code to target RAM - all within most industry standard debugger interfaces. Built-in memory tests assist in hardware testing. And the EPI open-source flash programming algorithm allows programming of flash memory located either internal or external to the SoC device. The MAJIC-MX probe expands to support additional cores, debug interfaces, or SoC devices. This eliminates the need to buy new emulators for each new project, thus reducing project costs. You may adapt the MAJIC-MX controller for operation with your specific processor or CPU cores by selecting from a wide range of configuration kits. The kits contain the firmware and user license to match your CPU's on-chip debug facilities. Install multiple configuration kits, and the MAJIC-MX probe will support a variety of CPU types. The MAJIC-MX controller is ready to run with the EPI software tools and any development board that supports a connection to the on-chip debug interface. This combination of tools will work together to provide you with a proven working environment. The MAJIC-MX controller is available as a stand-alone unit or as a complete debugging kit. The kit contains serial and Ethernet cables, source-level debugger, and one year of free maintenance, support, and updates. Part number: MAJIC-MX-KIT. Complete development kits are also available that include a compilation toolkit. See the EPI Price and Configuration Guide for full details of these development kits. Features of the MAJIC-MX probe include: Multi-Dimensional Scaling Support for SoC Devices MAJIC-MX probe embodies the new MDSS debug concept. This concept allows fast integration and debugging of software for complex SoC devices. To support SoC designs that are rapidly scaling up in both pipeline speeds and complexity, MAJIC-MX probe supports: Multi-tap devices, Multi-core devices, Multi-architecture environments, Multi-session debug, Multi-context CPUs, and On-chip trace buffers. Execution Tracing MAJIC-MX controller supports full execution tracing from CPU cores that offer on-chip trace buggers. Trace control allows tracing from start of execution or tracing up to a breakpoint. Ethernet Interface The 10/100 Ethernet interface provides many advantages over serial or parallel interfaces to the host. Download of your application code is over ten times faster than with serial interface. This will significantly reduce the amount of time spent waiting for code changes to download to your target board. Network connection allows remote operation of the MAJIC-MX probe. Now you can access the lab setup directly from your desktop. This allows multiple engineers to share a common test bench. Flash Memory The firmware of a MAJIC-MX probe is easily upgraded without the need to replace ROMs. Quickly install new configuration kits to add support for multiple CPU types and easily program IP address into the unit for point-to-point Ethernet operation. Internal RISC Processor A high-performance internal RISC processor provides fast response to debugger operations, such as single-stepping and downloading code to the target. Programmable JTAG Clock The MAJIC-MX probe features a programmable TCK with a 0 to 40 MHz range. This allows you to tailor the JTAG operation to match the performance of your target. It also means that you can use the MAJIC-MX probe with low-speed ASIC emulators, with FPGA implementation of your SoC design, or with devices that feature sleep-mode operation. Convenient Reset Switch A convenient reset button on the MAJIC-MX probe is protected against accidental activation, yet is easily accessible by the user when a complete system reset is desired. Programmable Trigger Control The MAJIC-MX probe gives you control over both the trigger-in and trigger-out signals. The trigger-in signal may be used to create a breakpoint or synchronize execution. A trigger output may set to indicate execution status, indicate memory accesses, or indicate a memory test failure. Status LEDs The MAJIC-MX probe provides five LEDs, which show the operational status of the controller. These LEDs also indicate the results of the built-in self-test that is automatically performed upon startup. International Power Supply The MAJIC-MX probe operates from a standard 5V power source. It comes with an external UL/CE-approved AC adapter, whose AC input range is compatible with all international AC voltage and frequency ranges. A standard three-wire power connector is compatible with readily available power cords through the world. Specifications: MAJIC-MX probe JTAG clock(TCK): 0 to 40 MHz, Programmable Download speed: >100k bytes/sec (typical) Target voltage: 1.8 to 5.0V Serial interface: RS232C at 1900-115.2K baud Ethernet interface: 10/100Base-T, TCP/IP Triggers: Trigger input Trigger output Trigger Control Trigger In: Off, run sync, break Trigger Out: Off, run sync, memory access, memory test error Trigger Levels: TTL Indicator LEDs: Power, status, run, connect, Ethernet Size (inches): 2.0 H x 7.4 W x 6.5 L Weight: 2.25 lbs Input power: 5 VDC +/- 5%, 4.0 A Power connector: 2.1 mm coaxial, center positive, male Temperature: 0 - 40 degrees C (Operating) Humidity: 15% - 95% RH (Operating) Safety/EMC: CE Item is in good physical condition and came from a working business that closed. Item powers up. Auction Includes power adapter Jtag cable, users/programmers manual. Don't forget to place your bid. By bidding on this auction you agree to the following terms: Shipping Terms: Buyer pays all shipping costs. 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